1. Technical Field
The present invention relates to a semiconductor memory apparatus, a semiconductor integrated circuit having the same, and a method of outputting data in a semiconductor memory apparatus. In particular, the present invention relates to a semiconductor memory apparatus that increases a time margin between output data and a data output strobe signal, a semiconductor integrated circuit having the same, and a method of outputting data in a semiconductor memory apparatus.
2. Related Art
Generally, in a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) and a semiconductor memory apparatus more advanced than the DDR SDRAM, data is output at rising and falling edges of a clock, respectively. To this end, a DLL (Delay Locked Loop) circuit generates a rising clock having a high-level period at a rising edge of an external clock and a falling clock having a high-level period at a falling edge of the external clock. A data output circuit of the semiconductor memory apparatus latches rising output data and falling output data in response to the rising clock and the falling clock, then sequentially buffers the rising output data and the falling output data, and subsequently outputs them as the output data DQ. Further, the data output circuit generates the data output strobe signal DQS from the rising clock and the falling clock and outputs the generated data output strobe signal DQS. Subsequently, a memory control apparatus that controls the semiconductor memory apparatus performs a data recovery operation using the data output strobe signal.
Hereinafter, the operation of a data output circuit in a semiconductor memory apparatus according to the related art will be described with reference to FIG. 1.
FIG. 1 is a timing chart illustrating a data output operation in a semiconductor memory apparatus according to the related art. In FIG. 1, the burst length is, for example, 4.
FIG. 1 shows a rising clock rclk and a falling clock fclk generated by a DLL circuit, output data DQ, and a data output strobe signal DQS. The four output data DQ successively output are alternately synchronized with the rising clock rclk and the falling clock fclk. The data output strobe signal DQS has the same waveform as the rising clock rclk during a period in which the output data DQ is output.
As such, the data output circuit in the semiconductor memory apparatus according to the related art sequentially buffers data latched by the rising clock rclk and the falling clock fclk, outputs the data as the output data DQ, and generates the data output strobe signal DQS from the rising clock rclk and the falling clock fclk. At this time, a time margin between the output data DQ and the data output strobe signal DQS, that is, a valid period tDV of one bit of the output data DQ corresponds to a half cycle of the rising clock rclk or the falling clock fclk. In order to improve a data output speed, a technology that reduces the swing width of data, and provides buffers, which generate output data DQ and inverted output data/DQ, and a data output strobe signal DQS and an inverted data output strobe signal/DQS, is used. In this case, however, the effective period of the output data DQ is not more than the half cycle of the clock.
Meanwhile, with an increase in execution speed of the semiconductor memory apparatus, the toggle speed of the rising clock rclk or the falling clock fclk and the output speed of the output data DQ are significantly increased.
However, since the toggle speed of the data output strobe signal DQS is also increased, the valid period tDV of the output data DQ is significantly decreased. This makes it difficult for the memory control apparatus, which controls the semiconductor memory apparatus, to restore the data. In addition, the valid period tDV of the output data DQ may be further decreased due to resistance and capacitance characteristics of the transmission line from the semiconductor memory apparatus to the memory control apparatus. Further, the valid period tDV of the output data DQ may be decreased due to various factors, such as a change in PVT (Process, Voltage, and Temperature) and the like. As described above, in the related art, it is difficult to secure a time margin between the output data and the data output strobe signal according to the increase in execution speed of the semiconductor memory apparatus.